Two methods that are repeatedly used during the fabrication of a microelectronics device are a lithography process to define a pattern in a photoresist layer and a plasma etch process to transfer the photoresist pattern into a substrate. Each new technology generation or node requires smaller features in the device pattern. These features are often filled with metal to form interconnects within and between different layers in a device. For example, in a dual damascene scheme, a trench opening is formed above a via hole in a dielectric layer and the two features are filled simultaneously with a metal such as copper or aluminum. The dielectric layer is an insulating material that typically consists of a low k dielectric material to prevent crosstalk between metal wiring. As the dimensions of the metal wiring and other device components shrink, a greater demand is placed upon the lithography and etch components of the manufacturing scheme to provide a process that is economical and reliable.
One aspect of the etching process that causes concern is charge build up on various parts of the plasma etch chamber including the upper surface of the pedestal or chuck to which a substrate is clamped during the etch step. The pedestal and clamp are usually comprised of a metal that is coated with an insulator such as quartz. However, charges can accumulate on the insulator that lead to arcing which may cause irreversible damage by dislodging portions of the substrate or forming holes in the substrate so as to render it unusable. Similarly, exposed parts within the etch chamber can become damaged by the arcing. Loss of substrates and downtime associated with repair of expensive etch equipment is quite costly. Therefore, a need exists for a means of preventing the arcing phenomenon within an etch chamber.
U.S. Pat. No. 5,292,399 describes an apparatus comprising a pedestal that has conductive plugs inserted in the upper surface to conduct charges away from a substrate. In addition, a quartz ring that surrounds the substrate on the exposed top surface of the pedestal is replaced with a conductive material such as graphite or silicide. A semiconductor material like silicon is preferred in some cases since it can be doped to adjust the resistivity of the ring or plug.
U.S. Pat. No. 6,251,792 claims an improved control of the plasma within an etch chamber by a design that includes a domed plasma reactor with an antenna that generates a high density, low energy plasma. The upper bias frequency is limited to prevent charge-up damage to sensitive devices.
As critical dimensions in devices shrink, the substrates on which the devices are fabricated tend to become larger. For example, state of the art fabs can now accommodate 300 mm wafers. In flat panel technology, large glass sheets can be difficult to process because of their size. In U.S. Pat. No. 5,895,549, a method is described for handling large substrates and an etch chamber is modified for etching at high power densities without causing arcing.
Other prior art which applies to an improved copper target for reducing defect generation during copper deposition by physical vapor deposition or high density plasma deposition is found in U.S. Pat. No. 6,139,701. This patent teaches the advantage of reducing surface roughness and using smaller Cu grain sizes to prevent arcing during plasma processing.
Arcing can result from several factors including local hot spots on a wafer, film charging, a high plasma current, and a strong local electrical field due to rough surface or improper layout. Additionally, etching, film deposition and photoresist development may cause charge build up on a substrate that leads to arcing.
A trend in the industry is the replacement of dielectric materials that have a relatively high k value such as SiO2 (k≃4) with materials that have a k value of about 2.5 or less. The introduction of these new materials presents a greater challenge to avoid arcing during plasma etching due to the poor thermal conductivity of the low k dielectric layers. Therefore, a method is needed that can prevent arcing in the presence of low k dielectric layers and with substrates which have an increased amount of metallization that is characteristic of newer technology generations. Preferably, an improved method is able to release a charge build up on a wafer that can occur for a variety of reasons. More preferably, the discharge process can be performed at different points in a multiple step etch process as a preventative measure for any etch step.